Analysis of 64- bit RC5 Encryption Algorithm for Pipelined Architecture

The RC5 Encryption Algorithm

This document describes the RC5 encryption algorithm, a fast symmetric block cipher suitable for hardware or software implementations. A novel feature of RC5 is the heavy use of data-dependent rotations. RC5 has a variable word size, a variable number of rounds, and a variable-length secret key. The encryption and decryption algorithms are exceptionally simple.

SPIM : A Pipelined 64 X 64 - bit Iterative Multiplier

A 64 X64-bit iterating multiplier, the Stanford Pipelined Iterative Multiplier (SPIM), is presented. Tbe pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a Wallace tree for a VLSI implementation because it is a more regular structure. A 4:2 carry-save accumulator at the bottom of the array is used to iteratively accumulate partial products, allowing a p...

On Differential and Linear Crytoanalysis of the RC5 Encryption Algorithm

This paper analyzes the security of the RC5 encryption algorithm against differential and linear cryptanalysis. RC5 is a new block cipher recently designed by Ron Rivest. It has a variable word size, a variable number of rounds, and a variable-length secret key. In RC5, the secret key is used to fill an expanded key table which is then used in encryption. Both our differential and linear attack...

On the Security of the Rc5 Encryption Algorithm

Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture

This paper describes the implementation of the Advanced Encryption Standard (AES) for a specific hardware architecture, which was developed based on the combination of different design paradigms. The architecture comprises synchronous and systematic bit–serial processing without a central controlling instance. To realize the AES cipher, we extended the architecture by designing specific element...